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Document Number: 325120-001Intel® Xeon® Processor E7-8800/4800/2800 Product FamiliesDatasheet Volume 2 of 2April 2011

Introduction10 Datasheet Volume 2 of 2 IOH Input/Output Hub. An Intel® QuickPath Interconnect agent that handles IO requests for processors.IPI Inter-

Datasheet Volume 2 of 2 11Introduction1.3 Notational Conventions1.3.1 Hexadecimal and Binary NumbersBase 16 numbers are represented by a string of hex

Introduction12 Datasheet Volume 2 of 2

Datasheet Volume 2 of 2 13Intel Xeon Processor E7-8800/4800/2800 Product Families Architecture2 Intel Xeon Processor E7-8800/4800/2800 Product Familie

Intel Xeon Processor E7-8800/4800/2800 Product Families Architecture14 Datasheet Volume 2 of 2 2.1.1 Intel® Xeon® Processor 7500 Series-Based Platform

Datasheet Volume 2 of 2 15Intel Xeon Processor E7-8800/4800/2800 Product Families Architecture2.2 Intel Xeon Processor E7-8800/4800/2800 Product Famil

Intel Xeon Processor E7-8800/4800/2800 Product Families Architecture16 Datasheet Volume 2 of 2 §Figure 2-2. Intel® Xeon® Processor E7-8800/4800/2800 P

Datasheet Volume 2 of 2 17Address Map3 Address Map3.1 NodeID GenerationIntel Xeon processor 7500 series system addresses are made up of a socket and a

Address Map18 Datasheet Volume 2 of 2 3.1.2 I/O Decoder MapTab l e 3-3 shows the I/O decoder address map. Given for each region are the name, the pat

Datasheet Volume 2 of 2 19Address MapIn the Addr field, letters have the following meaning:• "x...x": match any value• "aaaa": mat

2 Datasheet Volume 2 of 2 Legal Lines and Disc laimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS

Address Map20 Datasheet Volume 2 of 2 — Attempts to insert non-trusted VMM (rootkit hypervisor) Reset attacks designed to compromise platform secrets

Datasheet Volume 2 of 2 21LLC Coherence Engine (Cbox) and Caching Agent (Sbox)4 LLC Coherence Engine (Cbox) and Caching Agent (Sbox)The Intel Xeon Pro

LLC Coherence Engine (Cbox) and Caching Agent (Sbox)22 Datasheet Volume 2 of 2 4.1.1 LLC Major Features•Cache size:— 30 MB for ten Intel Xeon Processo

Datasheet Volume 2 of 2 23LLC Coherence Engine (Cbox) and Caching Agent (Sbox)Note: During power-on before Non-coherent (NC) freelist is available and

LLC Coherence Engine (Cbox) and Caching Agent (Sbox)24 Datasheet Volume 2 of 2

Datasheet Volume 2 of 2 25Home Agent and Global Coherence Engine (Bbox)5 Home Agent and Global Coherence Engine (Bbox)Each Intel Xeon Processor E7-880

Home Agent and Global Coherence Engine (Bbox)26 Datasheet Volume 2 of 2 5.1.1 The Tracker ModesThe tracker modes (0..3) are specifically chosen to sup

Datasheet Volume 2 of 2 27Home Agent and Global Coherence Engine (Bbox)Note: TID Assignment Restrictions have been updated for modes 4, 5, 6, and 7.5.

Home Agent and Global Coherence Engine (Bbox)28 Datasheet Volume 2 of 2 IODC is supported only in 4 socket configurations with 2 IOH or less. It is al

Datasheet Volume 2 of 2 29System Configuration Controller (Ubox)6 System Configuration Controller (Ubox)The Intel Xeon Processor E7-8800/4800/2800 Pro

Datasheet Volume 2 of 2 3Contents 1Introduction...

System Configuration Controller (Ubox)30 Datasheet Volume 2 of 2

Datasheet Volume 2 of 2 31Memory Controller (Mbox)7 Memory Controller (Mbox)The Intel Xeon Processor E7-8800/4800/2800 Product Families consists of tw

Memory Controller (Mbox)32 Datasheet Volume 2 of 2 Note: Memory Mirroring with tracker mode 6 is not supported.Note: RFR_FSM errors may be logged in t

Datasheet Volume 2 of 2 33Memory Controller (Mbox)7.5 Partial Memory MirroringPartial memory mirroring is a mirror mode of operation with parts of sys

Memory Controller (Mbox)34 Datasheet Volume 2 of 2 Note: The overall system configuration will resemble a full memory mirror configuration that has g

Datasheet Volume 2 of 2 35Memory Controller (Mbox)7.5.2.1 Pre-conditions• Assumes Master/Slave with identical memory types, and density.• Assumes exis

Memory Controller (Mbox)36 Datasheet Volume 2 of 2 characteristics like power consumed/saved, entry latency, exit latency. Memory contents may be reta

Datasheet Volume 2 of 2 37Physical Layer (Pbox)8 Physical Layer (Pbox) The Intel Xeon Processor E7-8800/4800/2800 Product Families have two fully buff

Physical Layer (Pbox)38 Datasheet Volume 2 of 2 Figure 8-1 shows the interface of each of Pbox instances with other uncore boxes. PZ0 and PZ1 are the

Datasheet Volume 2 of 2 39Power Management Architecture (Wbox)9 Power Management Architecture (Wbox)The power management control unit, (Wbox), control

4 Datasheet Volume 2 of 2 9.1.1 Thermal Monitoring - 2 (TM2)...399.1.2 Thermal Monitor

Power Management Architecture (Wbox)40 Datasheet Volume 2 of 2 9.1.3 THERMTRIP# All thermal sensors, including the uncore thermal sensor, have a catas

Datasheet Volume 2 of 2 41Power Management Architecture (Wbox)referred to as ''C'' states. C0 refers to the processor active state

Power Management Architecture (Wbox)42 Datasheet Volume 2 of 2 9.2.2.1.1 Thread C-StatesEach thread in a core can request a transition to a C-state in

Datasheet Volume 2 of 2 43Power Management Architecture (Wbox)9.2.2.2 Package C-State ResolutionThe package must resolve the C-state requests of each

Power Management Architecture (Wbox)44 Datasheet Volume 2 of 2 If this is the last enabled thread to enter the C3 or lower state, the Intel Xeon Proce

Datasheet Volume 2 of 2 45Power Management Architecture (Wbox)defaults to having a sub-state of zero. However, I/O redirected MWAITs always assumes th

Power Management Architecture (Wbox)46 Datasheet Volume 2 of 2 9.4.1 IntroductionThe PMReq negotiation is done to enter package C6 state where uncore

Datasheet Volume 2 of 2 47Power Management Architecture (Wbox)9.5.2 PMReq Retry/CmpD Response Behavior9.5.2.1 PMReq Retry DeterminationRetries are the

Power Management Architecture (Wbox)48 Datasheet Volume 2 of 2 a. Messages initiated in response to a PMReq message from another node that indicates t

Datasheet Volume 2 of 2 49Power Management Architecture (Wbox)Intel Xeon Processor E7-8800/4800/2800 Product Families expects mailbox sideband limit r

Datasheet Volume 2 of 2 5Revision History§Document NumberRevision NumberDescription Date325120 001 • Initial release of the document. April 2011

Power Management Architecture (Wbox)50 Datasheet Volume 2 of 2

6 Datasheet Volume 2 of 2

Datasheet Volume 2 of 2 7Introduction1 IntroductionThe Intel® Xeon® Processor E7-8800/4800/2800 Product Families is the second-generation chip multipr

Introduction8 Datasheet Volume 2 of 2 — Support for up to 16 DDR3 DIMMs per socket. Four DIMMs per Intel 7500 Scalable Memory Buffer— Support for DDR

Datasheet Volume 2 of 2 9Introduction• Execute Disable Bit capability• Direct-attach firmware to processor socket via serial flash interface— Supports